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DDR DFI Assertion IP

Overview

DDR DFI Assertion IP provides an efficient and smart way to verify the DDR DFI designs quickly without a testbench. The SmartDV's DDR DFI Assertion IP is fully compliant with standard DFI 2.0 or higher Specification.

DDR DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with DFI version 2.0 or higher Specification.
    • DFI-DDR Applies to :
    • DDR protocol standard JESD79F Specification
    • Supports all Interface Groups.
    • Supports Write Transactions with Data mask.
    • Supports Read data burst interruption
    • Supports Data bit enable/disable feature.
    • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
    • Supports Low power control features.
    • Supports Error signaling.
    • Supports DFI Read/Write Chip Select.
    • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
    • Constantly monitors DFI behavior during simulation
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DFI VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DFI Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

DDR DFI Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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