The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3.1 specifications and is fully backward compatible with CXL 3.0, 2.0, 1.1, and 1.0 specifications.
Panmnesia’s CXL IP consists of Panmnesia CXL Controller IP and PanmnesiaCustom CXL Logic. The Panmnesia CXL Controller IP supports all operations which are required
to communicate based on CXL specification, by sustaining all CXL subprotocols, including CXL.cache, CXL.mem, and CXL.io. On top of this foundational layer, PanmnesiaCustom CXL Logic enables various system devices to manage and access memory space based on the CXL specification.
CXL (Compute eXpress Link) 3.1 IP
Overview
Block Diagram

Technical Specifications
Foundry, Node
Any
Related IPs
- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- CXL 3.1 Controller
- Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
- GPU IP - Advanced graphics and compute acceleration for power constrained devices
- CXL 3 Controller IP