CSMC 0.13um 1.2v/3.3v APLL
Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 100MHz to 300MHz. It contains a 1-32 input clock divider, a 1-64 feedback clock divider and a 1-8 output clock divider. By setting DM [4:0], DN [5:0] and DP [2:0] to different values according to different REFIN, CLK and CLKO will be locked at the multiples of the input frequency.
Key Features
- Process: CSMC 0.13um Logic 1P8M 1.2v/3.3v CMOS process
- Supply voltage: 1.2v±10%, 3.3v±10%
- Current: <3mA
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
- Two output clocks: - CLKO: standard output from the output divider /- CLK: output from the VCO directly
Technical Specifications
Foundry, Node
CSMC 0.13um
Availability
GDS Ready
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV