crystalless USB1.1 PHY
Overview
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives data via DP and DM and transfers data to USB1.1 core via RCV, VM and VP, capable of transmitting and receiving serial data at full speed (12M bit/s). The serial interface engine (SIE) controls the state of USB1.1 PHY through the OEN signal. When in receiving mode, it receives data at the USB1.1 PHY output RCV, VM and VP; when in transmitting mode, it drives the USB1.1 PHY input VPO and VMO. Please note that the IP can only be used as device in crystalless mode, but either host or device in crystal and PLL mode. And the maximum data package on DP/DM is 64 bytes, longer package isn’t supported.
Key Features
- Compliant with the USB1.1 standard:a) In crystalless mode: Supports full speed device only b)With external crystal and PLL: Supports full speed only, can be used as either host or device.
- Power Supply: 1.5v and 3.3v
- GSMC 0.13um low power 4P5M 1.5V/HV e-flash dual gate process
- Uses digital input/output to transmit or receive USB cable data
- Supports 12Mbit/s full speed serial data transmission
- Supports single-ended data interface
- Built-in level shift
- Built-in 1.5K pull-up and 15K pull-down resistors, with selectable connection with DP or DM
- Supports w/o crystal mode, generates 48M clock output in without crystall mode
Technical Specifications
Foundry, Node
130nm
Maturity
Silicon proven