Crest Factor Reduction IP Core

Overview

Crest Factor Reduction (CFR) is a technique for lowering a waveform’s power ratio from higher to average. It is used in wireless communications and other applications to restrict the dynamic range of signals being sent. The peak to average Rate of multi-user and multi-carrier signals is frequently high. CFR is frequently connected with Digital Pre-Distortion (DPD) in modern transmit chains, which functions as Linearized Power Amplifiers, allowing for optimal efficiency.

Key Features

  • simulation models in Structural Verilog and MATLAB and suggest CFR Coefficients developed by MATLAB Functions. System Verilog is the hardware description language used for both design and verification, together with the MATLAB model, which is used for both exploring design options and verifying the design against simulation results.

Benefits

  • System-configurable for use with single-channel, multi-channel, and mixed-mode transmission systems.
  • Compatible with digital pre-distortion (DPD) and envelope tracking technologies (ET).
  • The target resource footprint is small.
  • Clock-to-sample ratios of 1, 2, 3, 4, and 8 are configurable.
  • Power and frequency dynamics are supported.
  • Support for one, two, four, eight, and sixteen antennas.
  • Provides considerable PAPR reduction from a single iteration structure, reducing additional delay.

Block Diagram

Crest Factor Reduction IP Core Block Diagram

Technical Specifications

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Semiconductor IP