IP Catalog > Security IP > Other > CPU-less TLS1.3 Offload IP core for FPGA Acceleration

CPU-less TLS1.3 Offload IP core for FPGA Acceleration

Overview

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.

Our TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS Upload and Download with standard web server by pure hardware logic on FPGA.

Key Features

  • CPU-less & No external memory required
  • Key exchange : X25519
  • Derive key : HKDF with SHA384
  • Encryption/decryption : AES256GCM
  • Self-signed Certificate : RSA2048
  • Support Ethernet speed 1G/10G/25G and 100G

Block Diagram

CPU-less TLS1.3 Offload IP core for FPGA Acceleration Block Diagram

Applications

  • Aerospace Telemetry: Ensure the integrity and confidentiality of sensitive inflight data streams from remote sensors in aerospace applications. FPGA-accelerated TLS 1.3 outpaces software-only solutions, safeguarding critical flight information. Read more
  • Medical Device Connectivity: Protect patient data in transit between medical devices and healthcare systems. Our solution provides the robust encryption and authentication mechanisms needed to comply with stringent healthcare regulations and safeguard patient privacy. 

Technical Specifications

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