CPRI Synthesizable Transactor provides a smart way to verify the CPRI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's CPRI Synthesizable Transactor is fully compliant with standard CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0 and provides the following features.
CPRI Synthesizable Transactor
Overview
Key Features
- Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
- Supports complete CPRI Tx/Rx functionality.
- Supports the Physical link layer (Layer 1) of the CPRI specification.
- Supports different standard line bit rates of the CPRI specification
- 614.4 MBPS
- 1228.8 MBPS
- 2457.6 MBPS
- 3072.0 MBPS
- 4915.2 MBPS
- 6144.0 MBPS
- 8110.08 MBPS
- 9830.4 MBPS
- 10137.6 MBPS
- 12165.12 MBPS
- 24330.24 MBPS
- Supports scrambler as in CPRI specification with enabling and disabling.
- Supports insertion of scrambler errors.
- Support disparity and invalid code insertion in 8B/10B.
- Supports 8B/10B line coding for bit rates upto 9830.4.
- Supports 64B/66B line coding without RS-FEC for 8110.08, 10137.6, 12165.12 and
- 24330.24 bit
- Supports 64B/66B line coding with RS-FEC for 24330.24 bit rate
- RS-FEC with alignment marker and without scrambler support
- RS-FEC without alignment marker and with scrambler support
- RS-FEC without alignment marker and without scrambler support
- Performs CPRI Hyperframe Framing
- Performs interleaving of IQ data, sync, C&M data, and vendor specific information
- Provides an 8-bit, 16-bit, or 32-bit for IQ data
- Performs sub channel mapping:
- Supports a slow C&M channel based on a serial HDLC interface for following standard HDLC bit rates
- - 240 KBPS
- - 480 KBPS
- - 960 KBPS
- - 1920 KBPS
- - 2400 KBPS
- - 3840 KBPS
- - 4800 KBPS
- - 7680 KBPS
- - HDLC bit rate negotiated on higher layer
- Supports a fast C&M channel based on a serial Ethernet interface
- Performs synchronization and timing.
- Supports the L1 Inband Protocol.
- Provides a parallel interface for merging vendor specific data into the CPRI frame.
- Provides a start-up sequence state machine in hardware for both REC and RE nodes
- which performs:
- L1 Synchronization
- Protocol setup
- C&M Plane setup
- Supports Link Maintenance
- LOS detection
- LOF detection
- RAI indication
- SDI indication
- Detects and reports the following errors
- Invalid control character
- Invalid data character
- Invalid 10bit code
- Scrambler errors
- Disparity errors
- Time division multiplexing errors
- Under and oversize frame
- CRC errors
- Framing errors
- LOS and LOF error injection
- Block sync bits error
- Block encoding error
- RS-FEC alignment marker error
- RS-FEC parity error
- Supports glitch insertion and detection
- Supports bus accurate timing and timing checks
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the CPRI testcases
- Examples showing how to connect and usage of Synthesiable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes