CPRI CONTROLLER IIP

Overview

CPRI CONTROLLER interface provides full support for the two-wire CPRI CONTROLLER synchronous serial interface, compatible with CPRI specification. Through its CPRI CONTROLLER compatibility, it provides a simple interface to a wide range of low-cost devices. CPRI CONTROLLER IIP is proven in FPGA environment.The host interface of the CPRI CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

CPRI CONTROLLER IIP is supported natively in Verilog and VHDL

Key Features

Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
Complete CPRI Tx/Rx functionality.
Supports the Physical link layer (Layer 1) of the CPRI specification.
Supports different standard line bit rates of the CPRI specification

614.4 MBPS
1228.8 MBPS
2457.6 MBPS
3072.0 MBPS
4915.2 MBPS
6144.0 MBPS
8110.08 MBPS
9830.4 MBPS
10137.6 MBPS
12165.12 MBPS
24330.24 MBPS

Supports scrambler as in CPRI specification.
Scrambler can be enabled or disabled.
Supports 8B/10B line coding for bit rates upto 9830.4.
Supports 64B/66B line coding without RS-FEC for 8110.08, 10137.6, 12165.12 and 24330.24 bit rates.
Supports 64B/66B line coding with RS-FEC for 24330.24 bit rate

RS-FEC with alignment marker and without scrambler support
RS-FEC without alignment marker and with scrambler support
RS-FEC without alignment marker and without scrambler support

Performs CPRI Hyperframe Framing

Performs interleaving of IQ data, sync, C&M data, and vendor specific information
Provides an 8-bit, 16-bit, or 32-bit for IQ data

Performs subchannel mapping:

Supports a slow C&M channel based on a serial HDLC interface for following standard HDLC bit rates.
240 KBPS
480 KBPS
960 KBPS
1920 KBPS
2400 KBPS
3840 KBPS
4800 KBPS
7680 KBPS
HDLC bit rate negotiated on higher layer
Supports a fast C&M channel based on a serial Ethernet interface.

Performs synchronization and timing
Supports the L1 Inband Protocol
Provides a parallel interface for merging vendor specific data into the CPRI frame
Provides a start-up sequence state machine in hardware for both REC and RE nodes which performs:

L1 Synchronization
Protocol setup
C&M Plane setup

Supports Link Maintenance

LOS detection
LOF detection
RAI detection
SDI Indication

Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The CPRI Controller interface is available in Source and netlist products.
The Source product is delivered in plain text verilog or VHDL or SystemC source code
Integration testbench and tests
Scripts for simulation and synthesis with support for common EDA tools
Documentation contains User's Guide and Release notes.

Technical Specifications

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