Configurable Viterbi Decoder

Overview

Key Features

• Support for zero-tail and tail-biting Viterbi decoding algorithms.
• Configurable constraint length.
• Configurable trace-back depth.
• Configurable code rate and soft bits.
• Continuous or gapped input data streams.
• Fully parallel or resource based architectures for different gate count/speed combinations.
• Low decoder latency.
• Fully synchronous design using a single clock.

Block Diagram

Deliverables

• Synthesizable VHDL or Verilog code.
• C++ model for system simulation.
• Comprehensive test bench.
• Detailed user's guide.

Technical Specifications