Configurable System Tick Counter
Overview
The CC-SYSTICK-AXI is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA and ASIC technologies.
Key Features
- AMBA APB4-Lite bus
- Programmable system tick timer
- Configurable prescaler and period
- Configurable interrupts
- Stop in debug mode option
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Silicon and FPGA proven
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Block Diagram
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Technical Specifications
Availability
Now
UMC
Silicon Proven:
130nm