Configurable CAN Bus Controller IP with Flexible Data-Rate
Overview
The Controller Area Network (CAN) is widely used in automotive and industrial applications. The CAN FD is a freestanding controller for the CAN. The Bosch CAN 2.0B standard (2.0B Active) and the CAN FD (flexible data-rate) are both met by the CAN FD, which was created in line with ISO 11898-1:2015.The success of CAN is largely due to its sophisticated error detection features, which improve communication reliability, and its unique fault confinement, which ensures network-wide data consistency. Reliable implementations are essential due to their basic importance in all facets of security and safety. The enhanced protocol surpasses the limitations of the original may: data may be carried at a rate more than 1 Mbit/s, and the payload (data field) is no longer restricted to 8 bytes but can now be up to 64 bytes long. Because there is only one node sending, the data rate may be raised.
Key Features
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Support up to 64 bytes data frames
- Flexible data-rates supported
- Supports emotas CAN open FD stack
- 8/16/32-bit CPU slave interface with small or big endianness
- Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
- Data rate up to 8 Mbps
- Hardware message filtering (dual/single filter)
- 128 byte receive FIFO and transmit buffer
- Overload frame is generated on FIFO overflow
- Normal & Listen Only Mode
- Transceiver Delay Compensation up to three data bit long
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri-states
- Scan test ready
Applications
- Automotive
- Industrial
- Embedded communication systems
- Wireless
Deliverables
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- FPGA Netlist
- VHDL /VERILOG test bench environment
- Active-HDL automatic simulation macros
- NCSim automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery of the IP Core and documentation updates, minor and major versions changes
- Phone & email support
Technical Specifications
Foundry, Node
Independent
Maturity
In Production
Availability
Immediate