Compute Express Link (CXL) 3.1 Controller
Overview
The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io protocol and adds the CXL.cache and CXL.mem protocols specific to CXL. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic.
Key Features
- CXL Layer
- Implements the CXL.io, CXL.mem, and CXL.cache protocols
- Supports all three defined CXL device types
- Supports the PCI Express 6.1 base specification
- Supports the PIPE 6.x specification with 8-, 16-, 32-, 64- and 128-bit configurable PIPE interface width
- Supports operation at x16, x8, x4, x2, x1
- Supports Host, Device, Switch ports and Dual Mode/shared silicon
- Supports Low-latency CXL.mem flit encoder/decoder
- Supports Viral error containment
- Supports deferrable writes
- Supports Standard Intel CPI interface for CXL.mem and CXL.cache
- Supports Sync header bypass and drift buffer modes
- Supports All low-power states
- Supports CXL RAS features (including Viral and Data Poisoning)
- Supports CXL.mem peer to peer and extended metadata feature
- Supports Hot-Plug
- Supports Alternate Protocol Negotiation
- Supports RCiEP
- Supports Global FAM (G-FAM) for Type 3 Device
- Supports Back Invalidation
- Supports lopt low-latency mode
- Supports full datapath parity protection for CXL.cache and CXL.mem
- Integrity and Data Encryption (IDE)
- Implements the CXL 3.1 IDE spec. for CXL.cache/mem
- AES-GCM security supports CXL.mem/CXL.cache at full line rate and with zero latency
- AES-GCM security IP supports PCIe/CXL.io to near full line rate with low latency
Benefits
- Ultra-low Transmit and Receive latency
- Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
- Supports backwards compatibility to PCIe 6.1
- Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
- Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
- Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
- Merged Replay and Transmit buffer enables lower memory footprint
- RAS feature support beyond CXLspecification
- Architected to support ASIC and FPGA implementation with the same code base
Deliverables
- IP Files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI (Wizard)
- Full Documentation
- Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project and DC constraint files
- FPGA reference design
Technical Specifications
Foundry, Node
Any
Availability
Available