Color Space Converter

Overview

The DB1810 Color Space Converter IP Core transforms three color components from one color space to another. An image can be sourced in one color space, while more efficiently processed, stored, or transmitted in another space, while still more effectively displayed in a third color space.

Figure 1 depicts the DB1810 Color Space Converter IP Core embedded within an integrated circuit device. The DB1810 accepts X1X2X3 tri-stimulus components and converts them to color space Y1Y2Y3 components. Control & Status, including the transforms coefficients, can be programmed into optional DB1810 registers via a bus interface, or set as non-register fixed parameters at synthesis for a smaller VLSI footprint.

Key Features

X₁X₂X₃ and Y₁Y₂Y₃ input & output components (for example, X₁X₂X₃ = RGB input; Y₁Y₂Y₃ = Y’CrCb output) each at 8- or 10-bits, unsigned data type. Userselectable at 24- or 30-bit parallel or serial input / output.
Coefficients are 10-bit signed fractional data type & Summands are 17-bit Signed, integer data type
After conversion, each Y1Y2Y3 sample component can be truncated or roundedup, and saturated or clamped for overflow or underflow, respectively
User optional Slave Bus Interface for programming Control & Status Registers, which includes the converters coefficients or fixed parameters set at synthesis
Member of Digital Blocks’ Video Signal & Image Processing IP Core Family, which include the following:
- DB1800 - Standard Definition NTSC/PAL/SECAM Video Sync Separator
- DB1810 - Color Space Convert
- DB1820 - Chroma Resampler
- DB1825 - RGB to YCrCb Color Space Convert with 4:4:4 to 4:2:2 Chroma Resampler
- DB1830 - BT.656 Encoder
- DB1840 - BT.656 Decoder
- DB1892 - RGB to CCIR601/656 Encoder
On-Chip Interconnect Compliance (optional) – Avalon/Qsys, AXI, AXI4, AHB:
- Avalon Interface Specification (MNL-AVABUSREF-2.0)
- AMBA AXI Protocol Specification (V1.0)
- AMBA AXI4 Protocol Specification (V3.0)
- AMBA AHB Specification 2.0
- AMBA APB Specification 2.0
FPGA Integration Support:
- Altera Quartus II & Qsys / SOPC Integration & NIOS II EDS Reference Design
- Xilinx ISE Design Suite utilizing AMBA AXI4 & Embedded Development & Software Development Kits
ASIC / ASSP Design-In Support:
- Compliance to RTL Design & Coding Standards
- Digital Blocks Support Services
Fully-synchronous, pipelined architecture, synthesizable Verilog RTL core

Block Diagram

Deliverables

The DB1810 is available in FPGA netlist or synthesizable RTL Verilog, along with Synopsys Design Constrains, a simulation test bench with expected results, reference design, and user manual.

Technical Specifications

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