Color Space converter & Chroma Resampler- 4:4:4 RGB to 4:2:2 Y’CbCr

Overview

The DB1825 Color Space Converter & Chroma Resampler Verilog IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr color space followed by Chroma Resampling to 4:2:2 sampled Y’CbCr color components.

Figure 1 depicts the DB1825 Color Space Converter (CSC) & Chroma Resampler (CR) IP Core embedded within an integrated circuit device. Control & Status, including the CSC transforms coefficients and the CR decimating filters coefficients, can be programmed into optional DB1825 registers via a bus interface, or set as non-register fixed parameters at synthesis for a smaller VLSI footprint.

Key Features

User optional Slave Bus Interface for programming Control & Status Registers, which includes the converters coefficients or fixed parameters set at synthesis
Member of Digital Blocks’ Video Signal & Image Processing IP Core Family, which include the following:
- DB1800 - Standard Definition NTSC/PAL/SECAM Video Sync Separator
- DB1810 - Color Space Convert
- DB1820 - Chroma Resampler
- DB1825 - RGB to YCrCb Color Space Convert with 4:4:4 to 4:2:2 Chroma Resampler
- DB1830 - BT.656 Encoder
- DB1840 - BT.656 Decoder
- DB1892 - RGB to CCIR601/656 Encoder
On-Chip Interconnect Compliance (optional) – Avalon/Qsys, AXI, AXI4, AHB:
- Avalon Interface Specification (MNL-AVABUSREF-2.0)
- AMBA AXI Protocol Specification (V1.0)
- AMBA AXI4 Protocol Specification (V3.0)
- AMBA AHB Specification 2.0
- AMBA APB Specification 2.0
FPGA Integration Support:
- Altera Quartus II & Qsys / SOPC Integration & NIOS II EDS Reference Design
- Xilinx ISE Design Suite utilizing AMBA AXI4 & Embedded Development & Software Development Kits
ASIC / ASSP Design-In Support:
- Compliance to RTL Design & Coding Standards
- Digital Blocks Support Services
Fully-synchronous, pipelined architecture, synthesizable Verilog RTL core

Block Diagram

Deliverables

The DB1825 is available in FPGA netlist or synthesizable RTL Verilog, along with Synopsys Design Constrains, a simulation test bench with expected results, reference design, and user manual.

Technical Specifications

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