The CoaXPress standard defines a cost effective and easy interfacing between video devices and acquisition hardware over RG59 and RG6 coaxial cables. It enables hot-plug of devices and 24V power-over-cable with up to 13 Watts per cable.
A CoaXPress Device can support multiple cameras of many video stream formats. CoaXPress supports GenICam international standard, providing a generic programming interface for all kinds of cameras regardless of the interface technology.
Video streams are sent to a host at a selectable high-speed downlink connection rate from 1.25 Gbps to 6.25 Gbps per cable. Each device can transfer video streams over one or multiple cable connections; a quad-connection device can deliver a total throughput of 25 Gbps.
CoaXPress devices and cameras can be controlled from a host through the uplink connection at 20.83 Mbps. The CoaXPress standard also provides a low latency, accurate trigger interface between the devices and the host.
A CoaXPress Host can interface with one or more camera devices, each of one or multiple cables. The CoaXPress standard supports up to 256 video streams.
CoaXPress Multi-Link Multi-Stream Device
Overview
Key Features
- JIAA CXP-001-2013 CoaXPress 1.1 compliant
- Hardware-based Connection Management Dynamic Reconfiguration of bit-rate and active connections
- Selectable downlink connection rates, from 1.25 Gbps to 6.25 Gbps
- Up to 4 coaxial connections per Device IP
- Supports multiple video-streams, up to 256 independent stream IDs
- Supports all GenICam compliant image formats: rectangular and arbitrary shaped, area and line scan, single and multi tap, multiple regions of interest, all standard pixel formats
- Hardware-based CRC management and error-detection and recovery
- Trigger in/out interface with uplink latency of 3.4µs
- Optional 8in/8out GPIO interface compliant with JIIA NIF-001-2010 CoaXPress 1.0 standard
- AXI4-lite slave processor interface for application specific control between host and cameras
- Up to 4 AXI4-stream slave interfaces for video streams
- Xilinx7 series and UltraScale compatible, IP-XACT support
Block Diagram
Deliverables
- Single or multi-use license, encrypted source code or netlist
- Encrypted source code: VHDL RTL with synthesis scripts for Vivado
- Netlist: EDIF or Verilog
- Comprehensive documentation package: specification, integration, IP-XACT component, etc.
- Integration test-suite