USB 5G, 10G Host controller is a highly configurable core and implements the USB Host functionality that can be interfaced with third party USB PHY’s. For Product Brief and Datasheet of USB please contact us.The Host Controller core is architected with a high performance DMA engine in the xHCI Interface for maximizing performance.
The Host Controller core supports all mandatory and optional features of the xHCI power management interface. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB PHY for aggressive power savings required for mobile and handheld devices.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP etc. Optionally, it can be interfaced to standard PCIe core with optional virtualization support, for standard host adaptor implementations.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Our solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.
Certified USB 5G & 10G Host Controller
Overview
Key Features
- Compliant with xHCI Rev0.96
- Compliant with USB 5G, 10G Specification Rev1.0
- Implements Phy Logical/ Link / Protocol Layers.
- Asynchronous clocking between Host Controller and Application logic
- Supports Aggressive Low Power Management
- Configurable core frequency: 125, 250, 500 Mhz.
- Configurable PIPE Interface: 8, 16, 32 bit.
- Configurable Buffer Sizes.
- Configurable Host Controller Engine
- Support for normative optional features
- Support for multi-port implementation
- Flexible User Application Logic
- Can be used by any SoC / OCB interface.
- PCIe with optional IOV support
- Configurable Datawidth: 32, 64, 128 bit.
- Simple Register Interface for internal Register Access.
- Support for various Hardware and Software Configurability regarding Core characteristics.
Block Diagram
Deliverables
- Synthesizable Verilog RTL
- Configurable System Verilog Verification IP.
- Synthesis Scripts
- Documentation
Technical Specifications
Maturity
Silicon Realized, Golden Tree Demo available
Availability
Immediately