USB 5G, 10G and 2.0 Hub controller is a highly configurable core and implements the USB Hub functionality that can be interfaced with third party USB PHY’s. The Hub Controller core can be configured to support upto 15 downstream ports.
The Hub Controller core supports all defined USB power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB PHY for aggressive power savings required for bus powered hubs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Our solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications
Certified USB 5G & 10G, USB2 Hub controller
Overview
Key Features
- Compliant with USB2.0, 5G, 10G Specifications
- Configurable number of downstream ports
- Configurable Core Frequency
- Configurable Internal datapath width: 32, 64, or 128 bits
- Compliant with standard USB 3.0 PHY Interface
- Configurable PHY Interface width: 8, 16, or 32 bits
- Efficient buffering scheme for forwarding packets through hub with minimal latency
- Supports Bus and Self Powered Hub implementations
- USB 3.0 low power states support
- Extensive clock tree gating and multiple power well support for aggressive power savings
- Support for various Hardware and Software Configurability regarding Core characteristics
- Register Interface for internal Register Access
- Optional support for Compound Device Support
- Optional Support for USB2.0 Hub controller
Block Diagram
Deliverables
- Synthesizable Verilog RTL
- Configurable System Verilog Verification IP.
- Synthesis Scripts
- Documentation
Technical Specifications
Maturity
Silicon Realized