CAN Bus Controller with Message Filter (configurable)

Overview

Key Features

• Standard Compliant
• Full CAN 2.0B compliant
• Supports standard CAN baud rates including 1 Mbps
• 3 Programmable Acceptance Filters
• Message filter covers: ID, IDE, RTR, Data byte 1 and Data byte 2
• User selectable number of filters
• Receive Path
• 32 messages deep receive FIFO
• FIFO status indicator
• System time-stamp
• Transmit Path
• 16 messages deep transmit FIFO
• 1 message buffer for high priority messages to bypass transmit FIFO
• Message Arbiter
• System Bus Interface
• AMBA 2.0 Advanced Peripheral Bus Interface
• 8-bit, 16-bit, or 32-bit wide data path
• Status and configuration interface
• Programmable Interrupt Controller
• Local interrupt controller covering message and CAN error sources
• Supports FPGA systems with two clock domains
• System clock (fast clock)
• CAN clock (slow clock)
• Test and Debugging Support
• Listen only mode
• Internal loopback mode
• External loopback mode
• SRAM Based Message Buffers
• Optimized for low gate-count implementation
• 100% Synchronous Design

Benefits

• Several special implementation options are available for gate count optimized implementations. These options have to be configured prior to synthesizing the design.
• Configuration register read-back enable
• To minimize gate count, the configuration register read-back path can be disabled
• Receive and transmit FIFO size can be adapted to system requirements
• Two separate clock domains
• A dedicated CAN clock is available when the system clock is too high for the CAN core. This feature can be disabled by a configuration entry.
• Fixed configuration
• For gate count optimized FPGA implementations, it might be desirable to set the configuration register to a fixed value.
• Message filter support
• 3 local message filters can individually be selected. This provides the option of having 0, 1, 2, or 3 CAN message filters available for the target application.
• Different Data Bus Interfaces
• Supports 32-bit APB, 16-bit, and 8-bit system bus interfaces

Block Diagram

Deliverables

• VHDL or Verilog RTL Source Code
• Verification Suite
• Functional Testbench including CANbus tranceiver model and additional CAN nodes
• Synthesys Script
• Data Sheet
• User Guide
• Hotline Support by means of phone, fax and e-mail

Technical Specifications