Camera Link Interface

Overview

The Camera Link® IP Core is a high-speed LVDS transmitter / receiver pair that conforms to the standard Camera Link protocol originally developed by National Semiconductor Corp®. The design is comprised of an independent transmitter and receiver that may be implemented separately or together as a single transceiver unit. The IP Core may be used in either the BASE, MEDIUM or FULL configurations as defined in the Camera Link specification. In general, each data lane can support around 500 Mbps per LVDS lane on basic FPGA and SoC devices. This gives a typical throughput of around 2 Gbps over the 4 data lanes (BASE), 4 Gbps over 8 lanes (MEDIUM) or 6 Gbps over 12 lanes (FULL).

Key Features

Separate Camera Link® Tx/Rx pair
Support for BASE, MEDIUM and FULL configs
Error checking for data misalignment at the receiver
Data rates of up to 500 Mbps+ per lane on basic FPGAs and SoCs
Uses the standard LVDS I/O resources available on FPGA and SoC
Compatibility and/or replacement for commercial SERDES LVDS ICs
Examples include: SN65LVDS*, SN75LVDS*, DS90CR*, DS90UR* and THC63LVD* series ICs

Benefits

Technology independent soft IP Core
Suitable for FPGA, SoC and ASIC
Supplied as human-readable source code
One-time license fee with unlimited use
Field tested and market proven
Any custom modification on request

Block Diagram

Applications

Real-time / low-latency video interfaces
Data streaming interfaces over cable or twisted pair
General purpose LVDS / SERDES applications

Deliverables

VHDL source-code (or Verilog on request)
Simulation test bench
Examples and scripts
Full pdf datasheet
One-to-one technical support
1-year warranty and maintenance

Technical Specifications

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