BCH Encoder/Decoder IP Core

Overview

Nand Flash write cycles are limited. An ECC detects and corrects failed operations, increasing the lifetime of the Nand Flash memory. For Nand Flash-based data storage, using an ECC is mandatory to ensure data validity. The powerful IPM-BCH is based on the BCH algorithm.

The BCH Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-BCH Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint.

Key Features

IPM-BCH for NandFlash Storage
- Up to 84 error-bits/block
- Configurable block size
IPM-BCH for short code
- Option to be full asynchronous
- Option to be in 3 clock cycles
Fully Configurable
- Latency
- Datapath
- Error number
- Packet size

Benefits

Full hardware implementation for maximum performance, encoding, error detection and correct
Balanced performance/gatecount
All Galois fields covered
Validated IP reducesTime-To-Market

Block Diagram

Deliverables

Verilog RTL source code.
Synthesis scripts for Xilinx, Altera and Design Compiler.
Technical documentation.
Simulation testbench, with error injection.
One year of maintenance and technical support.
Supported simulators
- MTI Modelsim.

Technical Specifications

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