This IP is a BCH code encoder and decoder designed for
storage application to address the reliability challenges. The
parameters can be customized.
BCH encoder and decoder for NAND FLASH
Overview
Key Features
- Parameter customizable
- AXI interface, easy integration
- High throughput with low complexity hardware
- Strong error correction performance
- Patented low complexity parallel encoder design
- High parallel decoder design with low complexity
- Chien search design
Benefits
- Parameter customizable
- AXI interface, easy integration
- High throughput with low complexity hardware
- Strong error correction performance
- Patented low complexity parallel encoder design
- High parallel decoder design with low complexity
- Chien search design
Applications
- NAND FLASH error correction
Deliverables
- Source Code for Matlab simulation
- Verilog HDL Source Code for En/Decoder IP
- IP Verification Environment
- FPGA Verification Environment Reference Design
- IP User Guide
- IP Test Documantation
- Integration support including consulting
Technical Specifications
Foundry, Node
TSMC, 28nm
Maturity
Silicon Proven