AXI4 Memory-Mapped to/from AXI4-Stream DMA

Overview

The AXI4-DMA IP core interfaces AXI4 data bus to provide data transfers from AXI4 Memory-Mapped port to AXI4-Stream port or the other way round thus serving as a Direct Memory Access controller.

The core is supplied as independent Memory-Mapped to Stream and Stream to Memory-Mapped single DMA channel modules each with its own AXI4-LITE slave. The modules operate in direct register mode, where control and status registers (CSR) are used to configure descriptors and trigger transfers from the host system. Data bus width, address width, burst length and other parameters are customizable at synthesis time, allowing flexible resource management and adjusment for diverse peripherals. Stream master and slave logic includes convenient data width converters supporting byte alligned 8, 16, 24, 32 and higher bit widths.

The EDI-AXI4-DMA core is provided as VHDL source or packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the package allowing the designer to adjust for different peripherals.

Key Features

AXI4 Memory-Mapped to AXI4-Stream/AXI4 Memory-Mapped to AXI4-Stream DMA

Independent AXI4 compliant single channel modules
AXI4-Lite port for access to control and status registers
Descriptors configured and transfers triggered from control registers in Direct Register Mode
End of transfers reported in status register
Packaged for Xilinx Vivado® IP Integrator

Synthesis Configuration Parameters

Data bus width (32 to 1024 bits)
Address bus (32 or 64 bits)
Maximum burst size (up to 256)
FIFO size
TLAST triggered interrupt
Stream width 8, 16, 24, 32 bits and higher

Block Diagram

Applications

The core is suitable for AXI4 interconnected systems with AXI4-Stream compatible peripherals, that require software triggered data transfers from shared memory. Data width converter with 24 and 48 bit capabilities is convenient for video processing data formats.

Deliverables

The deliverable includes the packaged core, a testbench with multiple test cases, a simulation and a thorough datasheet. The driver software is available freely under GPL license.

Technical Specifications

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