AXI to APB Bus Bridge

Overview

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one governing the AXI transactions, and one governing APB transactions.

The AXI to APB Bridge acts as an AXI Slave component, and an APB Master component in an AXI/APB subsystem. Typically, the AXI to APB Bridge has its AXI interface connected to a Slave component port on an AXI Channel/Interconnect module, and its APB interface connected to the Master component port on an APB Channel module.

Key Features

  • Translates AMBA® AXI transactions to APB transactions
  • Low latency
  • Low Gate Count
  • Supports APB 2.0 and APB 3.0 Signaling
  • Independent ACLK, PCLK pseudo-synchronous clocks

Block Diagram

AXI to APB Bus Bridge Block Diagram

Deliverables

  • Verilog Source
  • Complete Test Environment
  • AHB Bus Functional Model

Technical Specifications

×
Semiconductor IP