AVC Intra Encoder & Decoder

Overview

The H.264 Intra Frame Codec Core is a high performance & highly optimized video compression- decompression engine targeted primarily at FPGAs. It is complaint with ISO/IEC 14496-10 and ITU-T H.264 standard. It is well suited for various applications ranging from broadcast & professional video to high end consumer electronics.

The Codec design is fully autonomous and does not require any external processor to aid the codec operations. The encoder takes in the uncompressed video input and outputs encoded video in Elementary Stream (ES) format or optionally in Transport Stream (TS) format. The decoder takes in the ES/ TS & output is 20-bit YUV data with embedded sync.

The codec solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirement of end customer.

Key Features

  • Standard: H.264/MPEG-4 Part 10 & SMPTE RP 2027-2012
  • Profiles: Constrained Baseline, Main and High profies
  • Video Resolutions: Up to 1920x1080
  • Frame Rate: Up to 60 fps
  • Bit rate: CABAC Bitrate: Up to 110 Mbps
  • CAVLC Bitrate: Up to 225 Mbps
  • Chroma Format: Monochrome, 4:2:0 & 4:2:2
  • Precision: Bit depths from 8 to 10
  • Encoder Input: 20-bit YUV data with embedded sync
  • Encoder Output: 8-bit elementary stream or optional transport stream
  • Decoder Output: 20-bit YUV data with embedded sync
  • Latency: Ultra low latency of 10 ms
  • Codec Flavors: AVC-Intra Class 50/100
  • Upgrade Options: AVC Intra 200, XAVC & Intra Frame 4Kp60
  • FPGA: Xilinx Kintex Ultrascale, Kintex-7 & Virtex-6

Benefits

  • Fully standards compliant - tested with ITU-T & other industry standard test suites
  • Rate distortion optimization
  • CBR, VBR and Capped VBR rate control
  • Intra prediction supports all prediction modes & IPCM
  • Supports both CABAC and CAVLC Entropy coding
  • Optional two pass encoding
  • Extensive options to customize the source code via use of parameters
  • Supports progressive and interlaced formats
  • Support for MBAFF when encoding an interlaced source
  • Single chip solution with no processor requirement
  • Easy to integrate and hence faster time-to-market

Block Diagram

AVC Intra Encoder & Decoder Block Diagram

Applications

  • High quality video ingest and archiving
  • Video playout servers
  • Low Latency Video Contribution
  • Test & Measurement Equipment’s
  • Aerospace & defense
  • Medical
  • Automotive

Deliverables

  • Source Code or Netlist
  • Simulation Model
  • Hardware Test Platform
  • Build Scripts
  • Test Reports
  • User Manual
  • Design Documentation
  • Constraint Files
  • Test Benches
  • Support for one year

Technical Specifications

Availability
Available
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Semiconductor IP