ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2

Overview

Key Features

• On-the-fly configuration, with each codeword:
• (a) LDPC/Turbo
• (b) All DVB-S2/S2X code rate (including Low-SNR)
• (c) Turbo interleaver parameters and codeword length per RCS/RCS2 decoder
• (d) Maximal number of iterations.
• 500MHz clock with RAD-hard cells (TSMC 65LP)
• Belief-propagation iterative decoding (floating-point performance)
• Single-port memories, external to the IP-core
• Options for synchronous or asynchronous reset
• Efficient HW utilization
• Indications on the number iterations done, early-convergence,
• and SNR
• Low power design:
• (a) Gated-clock registers and FF
• (b) All memories cs port is negated on clocks not used to access the memory
• (c) Continuous monitoring of convergence enables early stop of iterations when a codeword is found, or earlier if instructed due to system
• considerations.
• (d) idle signal enables powering- offthe whole IP-core
• Single clock synchronous design
• All IP-core inputs and outputs are registered
• Portable to all ASIC and FPGA technologies

Deliverables

• 1) Simulation bit-exact shared-object for Matlab/Octave/C/Cpp
• 2) Synthesizable Verilog HDL code
• 3) HDL test bench with vectors
• 4) Integration guidelines and datasheet
• 5) Support

Technical Specifications