ARC4 Stream Cipher Accelerators

Overview

The ARC4-IP-44 (EIP-44) is IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec) up to 5 Gbps @ 600MHz. Designed for fast integration, low gate count and full transforms, the ARC4-IP-44 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.

The ARC4-IP-44 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges up to 5 Gbps depending on the configuration and area. Gate count is about 7K to 32K gates depending on the configuration.

Key Features

  • Wide bus interface (32-bit data, 128-bit keys) or 32-bit register interface
  • Key sizes: 40 and 128 bits
  • Fully synchronous design

Benefits

  • High-speed ARC4 solution
  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Block Diagram

ARC4 Stream Cipher Accelerators Block Diagram

Applications

  • SSL
  • TLS

Deliverables

  • Documentation
    • Hardware Reference and Programmer Manual
    • Integration Manual
    • Verification Specification
  • Synthesizable Verilog RTL source code
  • Self-checking RTL test bench, including test vectors and expected result vectors
  • Simulation scripts
  • Configurations:
    • EIP-44a
      • Medium-speed
      • 6.9K gates
      • 3.55 bits/clk
      • up to 500 MHz
    • EIP-44b
      • High-speed
      • 6.3k gates
      • 6.4 bits/clk
      • up to 500 MHz
    • EIP-44c
      • Very High-speed
      • 30.9k gates
      • 8.0 bits/clk
      • up to 600 MHz

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP