The ARC-V™ RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applications where power & performance efficiency are key concerns. The DSP enhanced implementation (RMX-500D) adds DSP capability for applications such as IoT wearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.
The processors feature an efficient 5-stage Harvard architecture pipeline that provides excellent throughput for embedded applications.
The ARC-V RMX-500 features up to 64KB of Level 1 (L1) instruction & data cache and up to 2MB each of closely coupled instruction and data memories (CCM), maintain high code density and offer excellent performance within a very small footprint.
