AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. Pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output.
AR4JA LDPC decoder uses Min-Sum algorithm to perform decoding. Min-Sum algorithm is an iterative algorithm that progresses to convergence through two updates: check node update, and variable node update. Check node update is evaluated by calculating the minimums and signs of all connected variable nodes. Then variable node update takes place. Processing is done layer by layer until all layers and iterations are completed.
AR4JA LDPC Decoder
Overview
Key Features
- AR4JA LDPC code family is quasi-cyclic.
- Irregular parity check matrix.
- Run time configuration for more than one code rate (i.e., 1/2, 2/3 and 3/4).
- Configurable codeword size that supports 2K, 3K and 4k information words.
- Minimum sum algorithm.
- Layered decoding architecture.
- Soft decision decoding.
- Configurable iteration number.
- Synthesized on ASIC 40nm and Xilinx FPGA (Virtex-UltraScale VCU118).
- Compatible with “LOW DENSITY PARITY CHECK CODES FOR USE IN NEAR-EARTH AND DEEP SPACE APPLICATIONS, CCSDS 131.1-O- 2, September 2007” standard.
Applications
- Near-Earth and Deep-Space communication.
- Space links communication.
- Space Internet working services.
- FLASH Memory.
Deliverables
- Synthesizable Verilog.
- System model (Matlab).
- Verilog test bench.
- Comprehensive documentation.
Technical Specifications
Maturity
Mature
Availability
Immediate
TSMC
Pre-Silicon:
28nm
HPM