APB SPI (Serial Peripheral Interface) master and slave
Overview
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-SPI core can operate as a SPI master or slave. Multiple chip-selects are supported in master mode, to allow connection to multiple slave devices. The SPI is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.
Key Features
- Master or slave operation.
- Programmable word size (1 to 32 bits).
- Programmable bit ordering (MSB first / LSB first).
- Programmable clock polarity (CPOL) and phase (CHPA).
- Programmable bit rate.
- Automatic and manual chip-select generation.
- Multiple chip-select outputs.
- Configurable TX and RX FIFO.
- Configurable support for parallel as well as serial transfers.
- Supports multi-master and multi-slave operation.
- Auto TX and RX to reduce bus bandwidth requirements.
- AMBA 3 APB slave interface.
- DMA flow-control interface.
Block Diagram
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
- C API
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate
Related IPs
- Serial Peripheral Interconnect Master & Slave Interface Controller
- SPI Master / Slave Controller w/FIFO (APB Bus)
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- SPI Slave Serial Interface Controller
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa
- A bridge to convert the slave SPI interface to the master UART interface and vice versa