APB : The Advanced Peripheral Bus (APB) is used for connecting low bandwidth peripherals. It is a simple non-pipelined protocol that can be used to communicate (read or write) from a bridge/master to a number of slaves through the shared bus. The reads and writes share the same set of signals and no burst data transfers are supported. The latest spec is available on ARM website and is a relatively easy protocol to learn.
WASIELA uses APB to interface the MAC layer master to WASIELA’s PHY slave designs.
APB Slave
Overview
Key Features
- APB Salve.
- Configurable and customizable.
- Synthesized on ASIC 40nm TSMC and Xilinx FPGA.
- Compatible with AMBA standard.
Benefits
- Ease of integrating peripherals into large SOCs.
Applications
- APB Master.
- AXI Bus.
- SOC Designs.
Deliverables
- Synthesizable Verilog.
- System model (Matlab).
- Verilog test bench.
- Comprehensive documentation.
Technical Specifications
Maturity
Mature
Availability
Immediate
TSMC
Pre-Silicon:
28nm
HPCP
Related IPs
- I2C Master / Slave Controller w/FIFO (APB Bus)
- SPI Master / Slave Controller w/FIFO (APB Bus)
- I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
- I2C Slave Controller - Low Power, Low Noise Config with APB Interface
- I2C Slave Controller w/FIFO (APB Bus)
- I3C Master / Slave Controller w/FIFO (APB Bus)