AGC Control and data plane core
Overview
The eSi-AGC core provides the control and data plane interfaces to an AGC module. The signal processing in the core consists of a sliding energy estimate and saturation detection.
Key Features
- Sliding window energy estimator on IQ input samples
- Decibel conversion
- Clipping detection with median filter
- Configurable setpoint
- Configurable hysteresis to avoid hunting around the setpoint
- Configurable fast AGC descent on detecting regular clipping
- •un-time control of latency for input data following a change in AGC value
- AXI4-Streaming inputs and outputs
- APB configuration
- Verilog 2001
Benefits
- Simple standard interfacing
- Low-gate count
Applications
- Multi-standard wireless receivers
- Software defined radios (SDR) accelerator
- OFDM synchronization
Deliverables
- RTL
- Testbench
- Synthesis scripts
- Documentation
- MATLAB and C++ bit exact model
Technical Specifications
Foundry, Node
Any
Availability
Now
Related IPs
- AHB Channel with Decoder and Data Mux IP Core
- TwoFish data encryption and decryption
- ColdFire V1 core with EMAC, Divider and Cryptograhic unit
- ColdFire V2 Core with single Fast Ethernet and AMBA peripherals connected in a subsytem
- APB Channel with Decoder and Data Mux
- This is collection of Synchronization Components can be used to synchronize across different clock domains for control and Data Transfer