SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems main memory / DRAM. The IP implements the standard (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018). The SphinX family of cores covers a scalable IP with 128b and 256b key support, allowing the designer to choose the most efficient and effective core that satisfies the latency and throughput requirements.
The design is fully synchronous and supports independent, non-blocking encryption/decryption at main memory speed. SphinX is available for immediate licensing.
References:
IEEE Std 1619-2018, IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices https://standards.ieee.org/standard/1619-2018.html
NIST FIPS 197, Advanced Encryption Standard (AES) https://www.nist.gov/publications/advanced-encryption-standard-aes
AES-XTS encryption/decryption IP
Overview
Key Features
- AES-XTS mode
- 128b and 256b key support
- High speed (@DDR4/DDR5 speed)
- High throughput (@DDR4/DDR5 throughput)
- Low latency
- Independent, non-blocking encryption/decryption at main memory speed
- Modular and scalable architecture
- Key expansion integrated
- Fully synchronous
- Optional bypass mode
- Standard compliance (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018)
Benefits
- Main memory encryption/decryption (@DDR4/DDR5 speed)
- Independent non-blocking encryption and decryption
- No additional memory required
- Fully pipelined design, optimized for high throughput and low latency
- Operating at main memory speed and throughput (DDR4/DDR5)
Block Diagram
Applications
- Main memory (DDR4/DDR5) and other high performance storage devices such as NvMe, SSD, Optane and PCIe connected devices.
- Server
- Desktop
- AI
- ML
- Edge & Cloud
- Media & Entertainment
- Memory & Storage
- Automotive
- Defense
Deliverables
- Synthesizable Verilog RTL (encrypted)
- Implementation constraints
- UVM testbench (self-checking)
- Vectors for testbench and expected results
- User Documentation
Technical Specifications
Foundry, Node
TSMC 7nm
Maturity
Tape-out
Availability
Immediate
Related IPs
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR3 Controller IP
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- FlexNoC 5 Interconnect IP
- BCH Encoder/Decoder IP Core
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load