AES Crypto and SHA-2 Hash Core with DMA

Overview

The CRYPT-IP-120 combines local key storage, an AES cipher (AES-IP-39), a SHA-2 hash (HASH-IP-57) and DMA capability into an easy to integrate, silicon-proven package. Designed for fast integration into SoCs, and featuring low gate count and full transforms, the CRYPT-IP-120 DMA crypto engine provides a reliable and cost-effective embedded solution for high speed processing pipelines.

CRYPT-IP-120 Features

Specifications CRYPT-IP-120b CRYPT-IP-120c-c CRYPT-IP-120c-h CRYPT-IP-120d-h CRYPT-IP-120f
Control Interface Simple register based control interface
Operation done interrupt
DMA done interrupt
DMA Controller X X X X X

AHB Master & Slave Interfaces

X X X X X
Local Key Store X       X
AES X       X
SHA   224, 256 224, 256, 384, 512 224, 256, 384, 512 224, 256
Gate Count (fab and process node-dependent) 49-53K        

Key Features

  • The CRYPT-IP-120 DMA crypto core provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.
    • Significant performance boost compared to software execution on the host processor.
    • Ability to store keys in an integrated RAM via DMA, and keep these inaccessible from (but usable by) the host/application.
  • The flexibility of the CRYPT-IP-120 architecture allows customization to individual requirements, including SNOW3G, Kasumi, AES-XTS and other basic IP modules.

Benefits

  • Low-power Crypto core
  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP