AES-GCM Multi-channel upto 2Tbps Crypto Accelerator

Overview

The EIP-63, high speed AES-GCM engine is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data. Its flexible data path is suitable to scale from 100Gbps to 1.6Tbps to provide a tailored engine with minimal area for your application. The FIFO-like data interface makes it possible to perform frame processing for many different protocols, including MACsec, IPsec, OTN security. The multi-channel architecture makes it possible to alternate data processing for different channels or tunnels simultaneously. Block switching can be done with a granularity of a single clock cycle.
For AES-GCM H-key calculation, INSIDE Secure offers the EIP-36 AES-core IP with a 32-bit register interface. Alternatively, the H-key is calculated by the software.

Key Features

EXAMPLE CONFIGURATIONS
The SafeXcel-IP-63 has a scalable number of processing pipes and channels. It is available in different configurations, suitable for different applications to meet different gate count and throughput objectives.
• EIP-63a-c17-r
o single pipe, 17 channels, register based (no memories)
o 128 bits/clk
• EIP-63d-c4
o 4 pipes, 4 channels
o 512 bits/clk
• EIP-63f-c60
o 6 pipes, 60 channels
o 768 bits/clk
• EIP-63j-c120
o 10 pipes, 120 channels
o 1280 bits/clk

Benefits

PERFORMANCE AND CONFIGURATIONS
• Line rate performance without any restrictions.
• Throughput is solely determined by the data width and clock frequency. There are no bottlenecks or conditions that give back pressure / limit the throughput.
• Design achieves over 1.6 GHz in 16nm technologies.
• A configuration with 1280-bit bus processes at a rate of 2048 Gbit/s at 1.6 GHz.
MULTI-CHANNEL PROCESSING
• True multi-channel design with time-sliced processing.
• Single-slot calendar.
• Configurable to support up to 128 independent channels with different rates.
• Support for run-time channel and calendar reconfiguration.
• Channel rate is achieved by aggregating bandwidth of the time slots without limitations.
FRAME PROCESSING MODES
• AES-GCM mode
• En/decryption-only mode: AES-CTR.
• Authentication-only mode: AES-GMAC.
• Any size packet bypassing
FIPS CERTIFICATION
• Support for AES-CTR, AES-GMAC and AES-GCM transformations for FIPS certification of the crypto core.

Deliverables

Documentation:

Hardware Reference and Programmer Manual.
Integration Manual.

Synthesizable Verilog RTL source code.
Self-checking RTL test bench, including test vectors and expected result vectors.
Synthesis scripts.

Technical Specifications

Foundry, Node

Any

Availability

now

TSMC

Silicon Proven: 7nm , 16nm , 28nm , 40nm G

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