AES data encryption and decryption

Key Features

• Fully compliant with FIPS 197
• Key size of 128, 192 and 256 bits
• Encryption and Decryption
• Fully Synchronous Single Phase Design
• Key Expansion integrated
• no extra ROM and RAM required
• AMBA interface

Benefits

• ~ 5.500 gates Bare Core (incl. Subkeys, SBox)
• 2 cycles per bit @128 bit key
• 133MHz @0.25µm

Deliverables

• Synthesizable Verilog Source code
• Comprehensive verification test bench
• Synthesis Scripts (Synopsys)
• Documentation

Technical Specifications