AES bridge, a cryptographic coprocessor that complies with FIPS 197 Advanced Encryption Standard, employs the Rijndael encryption method to link APB, AHB, and AXI bus.
AES is a block cipher that is frequently used in security solutions, ranging from cloud servers to IoT devices. Performance and security are much improved when it is implemented in hardware as opposed to software.
Advanced Encryption Standard compliant with FIPS 197
Overview
Key Features
- Support for 128 and 256 key bit length
- Support for ECB, CBC, CFB, OFB, CTR block cipher modes
- Internal key expansion module
- Flexible data read/write modes
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus
Benefits
- Digital signature
- Data integrity
- Key derivation
- TLS/SSH/PGP IPsec communication
Deliverables
- Source Code:
- VERILOG test bench environment
- Technical documentation
- Synthesis scripts
- Example application
- Technical support
Technical Specifications
Maturity
In Production
Availability
Immediately
Related IPs
- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
- Advanced Encryption Standard En- / Decryption IP-Core
- Advanced Encryption Standard (AES-128) core with AMBA AHB interface
- Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard