Adjustable delay block for dual-phase regulator operation
Overview
Adjustable delay block for dual-phase regulator operation
Technical Specifications
Short description
Adjustable delay block for dual-phase regulator operation
Vendor
Vendor Name
Foundry, Node
TSMC 180nm
Maturity
Silicon Verified
TSMC
Pre-Silicon:
180nm
,
180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
,
180nm
LP
,
180nm
LV
,
180nm
ULL
Related IPs
- 256-steps adjustable delay cell
- TSMC 40nm LP combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- GF 22FDX combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
- ARC4 Core for Xilinx FPG
- Block Viterbi Decoder