9-bit 2-channel 0.5 to 33 MSPS (8 to 500 kHz BW) delta-sigma ADC

The block is second order delta-sigma ADC with 5-level quantizer.

The block consists of:
- two integrating cascades based on switch capacitors technique;
- 5-level flash-ADC;
- tunable (6-bit control) clock signal frequency divider;
- clock splitter;
- block of bias currents, tunable (6-bit control);
- Data-Weighted Averaging (DWA) correction of capacitors mismatch;
- input signal level detection.

Output signal is represented in “thermometer” code. There is a possibility to disable of each channel, frequency divider, block of bias currents, DWA correction. There is an in-built output from frequency divider for clocking digital filters.
Input DC level is 0.9 V; recommended voltage levels for references are 0.9 ± 0.4 V; recommended input signal differential amplitude is 0.64 V; allowable deviation of clock duty cycle: 50 ± 5%.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.