The W65C02S IP is a 8/16-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores. It is software compatible with the 8-bit NMOS and CMOS 6500-series predecessors.
The W65C816S extends addressing to a full 16 megabytes. A software switch in the Processor (P) status and mode register determines whether the processor is in 8-bit "emulation" mode or in native mode. The Accumulator, ALU, X and Y Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page register increases the flexibility and number of address and data pointers available with the Direct Page addressing modes (formerly Zero Page addressing) and supports both 16-bit and 24-bit pointer addressing. Separate Program Bank and Data Bank registers provide 24-bit memory addressing with segmented or linear addressing..
WDC's RTL Softcore version provides a cycle accurate option providing for implementation onto any foundry process.
Development tools are available for creation of 65xx application code.
8/16-Bit Microprocessor Core
Overview
Key Features
- Emulation mode allows complete hardware and software compatibility with 6502 designs
- 24-bit address bus provides access to 16 MBytes of memory space
- Full 16-bit ALU, Accumulator, Stack Pointer and Index RegistersValid
- ata Address (VDA) and Valid Program Address (VPA) output for dual cache and cycle steal DMA implementation
- Vector Pull (VPB) output indicates when interrupt vectors are being addressed
- Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions
- Separate program and data bank registers allow program segmentation or full 16 MByte linear addressing
- New Direct Register and stack relative addressing provides capability for re-entrant, re-cursive and re-locatable programming
- 24 addressing modes - 13 original 6502 modes with 92 instructions using 256 OpCodes
- Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further reduce power consumption, decrease interrupt latency and allows synchronization with external events
- Co-Processor (COP) instruction with associated vector supports co-processor configurations, i.e., floating point processors
- Block move ability
Benefits
- Flexible Licensing Options and Pricing Model
Deliverables
- GDSII Database, Verilog RTL, or FPGA Specific Post-Synthesis Netlist
- Simulation Test Benches, Results, and Documentation
- Assemly Test Files
- Datasheet Documentation
Technical Specifications
Foundry, Node
0.8u, .6u, .5u, .35u, .25u, .18u, .13u, 90nm
Maturity
GDSII Hard Core - 25 years; RTL Soft Core - 8 years
Availability
Now