50G/100G MAC/PCS/FEC

Overview

The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications is complaint with IEEE 802.3cd-2018 standard and Ethernet Technology Consortium 50GE standard. The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer and symbol distribution.

The north-bound interface from the MAC provides a configurable n x 64-bit system interface.

The southbound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management.

Key Features

  • Logic and power efficient KR4 and KP4 FEC engine with full warnings and alarms
  • Integrated 64B/66B and 256B/257B encoder for area efficiency 
  • Built-in loopbacks and PRBS generators/ checkers for test and diagnostics
  • Fully compatible with IEEE802.3 3cd-2018 Standard and Ethernet Technology Consortium 50GE Standard
  • Super low latency with minimized fixed and
  • variable delay for network efficiency.
  • Supports 1588v2 time stamps and full error handling
  • Supports 802.3br express traffic and 802.1Qbb priority flow control (PFC)

Benefits

  • Proven IP reduces development time and risk
  • Supports both 50GBASE-KR2/1 and 50GBASE-CR2/1 PMD interfaces
  • Support 25G NRZ SerDes and 56G PAM4 SerDes
  • Off-the-shelf, proven technology implementation in Altera and Xilinx FPGAs and ASIC SOC
  • Upgrade process as the standard evolves
  • Support both KR4 FEC (RS528,514) and KP4 FEC (RS544,514) modes
  • Support for 2-lane or single-lane SERDES interface
  • Tested and interoperability-proven against
  • Spirent and Viavi test equipment

Block Diagram

50G/100G MAC/PCS/FEC Block Diagram

Applications

  • High performance server network interface cards
  • Mid-sized routers

Technical Specifications

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Semiconductor IP