The block is fourth order cascade (2-2) delta-sigma ADC with 5-level quantizers in both stages. The block consists of:
- two delta-sigma modulators second order, coupled in series, in each channel
- clock generator
- bias current source
- voltage reference source
- CLA-, DWA-, BiDWA-correction of capacitors’ mismatch
- digital filter
ADC is designed for TSMC CMOS 65 nm technology using 6 levels of metal wiring.
5 MHz 14-bit 2 channel 300 kSPS cascade delta-sigma ADC
Overview
Key Features
- TSMC CMOS 65 nm
- Cascade (2-2) delta-sigma ADC
- Supply voltage from 1.3 V to 3.0 V
- Input differential signal range – 0.64 V
- LDO embedded
- Internal reference voltage generation (0.6 V ± 0.2 V)
Applications
- Analog to digital conversion of the signal
- Receivers, transceivers
- Measurement environment
- Medicine environment
Deliverables
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Verilog behavior model
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 65 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
65nm
G
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