The 3DES-IP-16 (EIP-16) is IP for accelerating the AES symmetric cipher algorithm (FIPS-46/81 – SP800-IP-20), supporting single Des and triple DES in ECB, CBC, CFB and OFB modes up to 4 Gbps @ 800MHz. Designed for fast integration, low gate count and full transforms, the 3DES-IP-16 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.
The 3DES-IP-16 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the 3DES-IP-16 is the cipher core embedded in all IPsec protocol aware security engines. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Sustained performance for any object sizes ranges up to 4 Gbps depending on the configuration and area. Gate count is between 9K and 15K gates depending on the configuration. Multiple 3DES-IP-16 cores can be cascaded.
