32-bit RISC-V microcontroller

Overview

Key Features

• Configurable instruction set architecture:
  • 32-bit RISC-V with 32 integer registers (I extension)
  • Integer multiplication and division (M extension)
  • Compressed mode for better code density (C extension)
  • Atomic operation support (A extension)
  • IEEE 754-2008 compliant single precision floating point (F extension)
  • IEEE 754-2008 compliant double precision floating point (D extension)
  • User-level interrupt support (N extension)
  • Bit manipulation instructions support (B extension)
  • Scalar cryptography instructions support (K extension)
  • Digital signal processing instructions support (P extension)
• Machine and User modes
• 2-3-stage pipeline
• Configurable branch predictor
  • Static: may be used to optimize area
  • Dynamic (micro-BTB): may be used to optimize performance
• Optional instruction cache to accelerate access to slow memory
• Configurable interrupt subsystem
  • Platform Level Interrupt Controller (PLIC)
  • Core Local Interruptor (CLINT): timer + software
  • Local interrupt support to provide fast handling
  • Core Local Interrupt Controller (CLIC)
  • Non-Maskable Interrupts (NMIs)
• ECC memory protection (SEC-DED)
• Physical memory protection
• Integrated debug controller including HW breakpoints
• System bus access
• Compact JTAG support
• Trace support
• Power management support
• Configurable external interface: AHB-lite, AXI4
• Performance
  • 1.83 DMIPS/MHz
  • 4.0 CoreMark/MHz
• Frequency
  • Up to 700 MHz (TSMC, 28nm HPC+, 9t, SVT, SSG corner)

Block Diagram

Technical Specifications