32-bit High Performance Single/Multicore RISC System-on-Chip

Overview

The CC100-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip. The model is highly configurable and embeds a wide range of peripherals. The SoC can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

Key Features

  • High Performance 32-bit RISC CPU
  • Proprietary 6-stage pipeline
  • Single or multicore implementation
  • Up to 1.37 DMIPS/MHz/Core
  • Up to 2.29 CoreMark/MHz/Core
  • Optional set-associative caches with data snooping
  • Power-down mode
  • On-chip debug support
  • FPGA and silicon proven
  • JTAG or 2-pin Serial Wire Debug
  • Wariety of digital and analog peripherals
  • On-chip clock/reset source
  • Optional PLL
  • Optional backup RTC domain

Benefits

  • Synthesizable RTL Verilog source code
  • Cycle accurate simulator
  • Custom instruction set extension
  • Mature free GNU-Based C/GDB toolchain
  • Full implementation and maintenance support with individual approach
  • Low-cost and flexible licensing
  • Embedded solution for low-power and low-footprint applications
  • Suitable for mobile, IoT and wearable devices

Block Diagram

32-bit High Performance Single/Multicore RISC System-on-Chip Block Diagram

Technical Specifications

Maturity
Silicon proven
Availability
Now
UMC
Silicon Proven: 130nm
×
Semiconductor IP