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3/5 Port Deterministic Ethernet IP Solution with TSN (Time Sensitive Networking)

Overview

TTTech Industrial’s Edge IP Solution is the simple way to add TSN (Time Sensitive Networking) Ethernet functionality to switched endpoint devices such as industrial controllers. Edge IP Solution includes IP core and associated software for fast and easy integration onto your FPGA enabling open, standard deterministic switching functionality

Key Features

  • Ports:
    • 3 to 5 ports; 10/100/1000 Mbit/s
  • Target:
    • Device Cyclone V SoC, Arria 10
  • Physical Interfaces:
    • MII, GMII, DMA for host
    • PPS (Pulse-Per-Second) output
    • Avalon slave interface for management register access
  • Reference Designs
    • TTTech Industrial Evaluation Board
    • Intel Arria 10 SoC Development Kit
  • Reference Design Adapters
    • MII, GMII, RMII, RGMII, SGMII,
    • 100BASE-FX, 1000BASE-X
  • TSN
    • IEEE 802.1AS Time Synchronization
    • IEEE 802.1Qbv Scheduled Traffic
    • IEEE 802.1Qbu Frame Preemption
  • IEEE 802.1Q
    • Port-based VLAN classification
    • Assignment to traffic class on ingress ports
    • Support for credit-based shaper (CBS)
  • Clock Synchronization
    • IEEE 802.1AS (including multi-time domain support)
    • IEEE 1588-2008 layer 2 one/two-step end-to-end transparent clock support
  • Configuration
    • NETCONF 1.0/1.1 (RFC 6241) including derived YANG models
      • IEEE 802.1Qbv Scheduled Traffic
      • IEEE 802.1Qbu Frame Preemption
      • IEEE 802.1Qcp Bridges and Bridged Networks (VLAN support)
    • SNMP v1/v2/v3 (RFC 3416) including MIB
  • Switching Engine
    • Store and forward architecture providing full cross-sectional bandwidth
    • 128 Kbit frame buffer per port
    • 4096 VLANs
    • 16 MAC address filters per port
    • Up to 4096 entry MAC address hash-based learning table
    • Up to 4096 policers per port
    • 8 traffic shapers per port (optional)
    • Static configuration of MAC addresses
    • Flow identification-based MAC addresses
    • Ingress rate-limiting on a per-port basis for unicast, multicast, and broadcast traffic
  • Operating System
    • Linux Kernel 4.9 LTS, LTSI (optional real-time patch)
    • Support for Linux net_dev, switch_dev, and PHC (PTP hardware clock)
  • Embedded Software
    • Linux kernel module
    • Native Linux interfaces / user space configuration library
    • Edge PTP in binary format for ARM – for IEEE 1588 / IEEE 802.1AS clock synchronization
    • MSTP including additions for engineered traffic (802.1Qcc)
    • Open source support for SNMP and NETCONF

Benefits

  • Fast, easy integration into planned and existing FPGA-based devices
  • Provides guaranteed low-latency communication for critical traffic
  • Includes the latest IEEE 802.1 Ethernet standards
  • Seamless compatibility with TTTech Industrial Slate XNS network scheduler and topology builder

Deliverables

  • Encrypted Qsys IP component including interface adapters to xMII
  • Software and device drivers for Linux
  • YOCTO based build system
  • Ready-made boot image
  • Reference design for the Evaluation Board
  • MIBs and YANG models
  • Getting started guide
  • Technical documentation

Technical Specifications

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