The 3.3V General Purpose I/O library provides bidirectional I/O,
isolated analog I/O, and a full complement of power cells along with
corner and spacer cells to assemble a complete pad ring by abutment.
An included rail splitter allows multiple power domains to be isolated
in the same pad ring while maintaining continuous VDD/VSS for
robust ESD protection.
? Programmable bidirectional GPIO
? Input-only buffer
? Isolated analog I/O
? Full complement of power, corner, and spacer cells
3.3V Wide-Range General Purpose Staggered I/O Pad Set
Overview
Key Features
- Bidirectional GPIO Driver Features
- ? Multi-Voltage (1.2V, 1.8V, 2.5V, 3.3V)
- ? LVCMOS / LVTTL input with selectable hysteresis
- ? Programmable drive strength (rated 2mA to 12mA)
- ? Selectable output slew rate
- ? Optimized for EMC with SSO factor of 8
- ? Open-drain output mode
- ? Programmable input options (pull-up/pull-down/repeater)
- ? Power-On Start (POS) capable
- ? Power sequencing independent design with Power-On Control
- In full-drive mode, this driver can operate to frequencies in excess of
- 100MHz with 15pF external load and 125 MHz with 10pF load.
- Actual frequency limits are load and system dependent. A maximum
- of 200 MHz can be achieved under small capacitive loads.
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 7nm
Maturity
Silicon Proven
Availability
Available Now
TSMC
Pre-Silicon:
7nm