3.3V Wide-Range General Purpose Staggered I/O Pad Set
Overview
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power cells along with the necessary support cells to construct a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key Features
- ? Multi-Voltage (1.8V, 2.5V, 3.3V)
- ? LVCMOS / LVTTL input with selectable hysteresis
- ? Programmable drive strength (rated 2mA to 12mA)
- ? Selectable output slew rate
- ? Optimized for EMC with SSO factor of 8
- ? Open-drain output mode
- ? Programmable input options (pull-up/pull-down/repeater)
- ? Power-On Start (POS) capable
- ? Power sequencing independent design with Power-On Control
- ? Fault tolerant cell provides fail-safe operation
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 40nm
Maturity
Silicon Proven
Availability
Available Now