The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment.
An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
* Programmable bidirectional GPIO
* Fault-tolerant programmable bidirectional GPIO
* Input-only buffer
* Isolated analog I/O
* Full complement of power, corner, and spacer cells
ESD Protection:
* JEDEC compliant
* 2KV ESD Human Body Model (HBM)
* 200 V ESD Machine Model (MM)
* 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
* JEDEC compliant
* Tested to I-Test criteria of ± 100mA @ 125°C
3.3V Wide-Range General Purpose I/O Pad Set
Overview
Key Features
- Multi-Voltage (1.2V, 1.5V, 1.8V)
- LVCMOS / LVTTL input with selectable hysteresis
- Programmable drive strength (rated 2mA to 12mA)
- Selectable output slew rate
- Optimized for EMC with SSO factor of 8
- Open-drain output mode
- Programmable input options (pull-up/pull-down/repeater)
- Power-On Start (POS) capable
- Power sequencing independent design with Power-On Control
- In full-drive mode, this driver can operate to frequencies in excess of 100MHz with 15pF external load and 125 MHz with 10pF load.
- Actual frequency limits are load and system dependent. A maximum of 200 MHz can be achieved under small capacitive loads.
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
SMIC 28nm
Maturity
Pre-Silicon
Availability
Available Now
SMIC
Silicon Proven:
40nm
LL