(2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
Overview
The LDPC IP is a specialized encoder and decoder for Low-density parity-check codes, specifically designed for the 802.3an standard. Within the IEEE 802.3an 10GBASE-T standard, the (2048,1723) RS-LDPC code has been integrated as the designated forward error correction technique.
Key Features
- Strong error correction performance
- Optimized method significantly lower the error floor at minimal cost
- High throughput with low complexity hardware
- Early termination technique
Benefits
- Simulation with Intel CPU / with Modelsim & Matlab / with CUDA GPU
- Xilinx FPGA proven with Vivado 2022.2
Applications
- ethernet phy
Deliverables
- Source Code for Matlab simulation and matrix information
- Source Code for fast simulation on Nvidia GPU
- Verilog HDL Source Code
- IP Verification Environment
- FPGA Verification Environment Reference Design
- IP User Guide
- IP Test Documantation
- Integration support including consulting
Technical Specifications
Foundry, Node
SMIC 28nm
Availability
NOW