1MHz-50GHz Programmable Prescaler - Divider by 1/2/4/8/16 in SiGe

Overview

The PMCC_DIV50G1_16 is a high speed (up to 50GHz) fully differential programmable divider IP block, designed using Jazz SiGe120 (SBC18HX) technology. Divider selectable coefficients are /1 (bypass), /2, /4, /8 and /16. Differential architecture ensures substrate and power supply noise immunity. Macro features optional 50 Ohm terminated input and output (except bypass mode) buffer. Built-in power-down mode enables power saving in case when block is not operated. Operation frequencies, I/O signal levels, control functions and features can be customized upon special agreement.

Key Features

Maximum input frequency: 50GHz
Supply voltage: 3.3V ±5%
Power consumption:

/ 1 : 24mW
/ 2 : 45mW
/ 4 : 68mW
/ 8 : 80mW
/16: 94mW

Fully differential architecture
Layout area: 200 x 100 um

Benefits

Applications:
Phase–locked loop (PLL) applications from DC to 50 GHz
Point-to-point and point-to-multipoint radios
Broadband test and measurement equipment
Radar, electronic warfare, avionics, and space

Deliverables

GDS II file
Netlist for Spectre simulation
Layout and Schematic (DRC & LVS) verification reports
Complete macro datasheet
Macro integration/application notes
Design kit and software related information
Optional deliverables are:

Library containing entire hierarchy of macro schematic and layout cells
Extracted views containing parasitic components from layout
Verilog-A model replicating macro functionally
Simulation test-benches
Optional components specific to macro: biasing, specialized I/Os, glue-logic, transmission lines etc.

Technical Specifications

Foundry, Node

TowerJazz, 180nm

Maturity

Silicon

Availability

Now

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